RSP s10l is a SoC cryptographic security chip with high performance, high security and high cost performance for the state secret market developed by the reconfigurable technology team of Tsinghua University. Its application scenario is oriented to cloud interconnection, edge computing network and back-end encryption and decryption of the Internet of things. It can provide high-speed cryptographic operation services with multi threading and multi card parallel processing for various security platforms to meet its requirements for digital signature / verification, asymmetric / symmetric encryption and decryption, data integrity verification The requirements of true random number generation, key generation and management ensure the confidentiality, authenticity, integrity and non repudiation of sensitive data.

S10l provides a highly integrated single-chip solution for mini PCIe and PCIe cipher card market.

model RSP S10L

working frequency Up to 500MHz

High speed interface Support pcle 2.0x1

Low speed interface GMIIx2

SPI Master x 2; Slave x 1;

SDIOx1;

UART X 2

GPIO x 16

12Cx 1

Virtualization VF x 32

storage space NOR flash 8MB

Internal RAM space 1MB;

Secure storage space 128KB;

TRNG support

PUF support

Algorithm support Symmetry algorithm: arc4 / DES / 3DES, AES / SM1 / SM4 (ECB, CBC, xcbc, CNTR, GCM, XTS)

Hash algorithm: support SHA1 / SM3 1 Sha2 (224 / 256 / 384 / 512)

Public key algorithm: support rsa1024 / rsa2048 / Sm2

Stream encryption algorithm: zuc / snow3g

State secret performance SM2 signature: 25000 times / second; SM2 signature verification: 10000 times / second; SM3/4: 2Gbps

High speed interface AES: 2Gbps

SHA1/2: 1Gbps

Rsa2048: 1 dry time / S; 20000 times / S

Package specification FCBGA 20mm x 20mm

working temperature 0°C - 70°C